Chetan Sheshikumar-RTL Design Engineer | Digital Design & Verification | SystemVerilog / Verilog | Freelance & Contract Availability

M.Sc. Electrical Engineering & Embedded Systems student and RTL design engineer with two years of full-time, professional RTL design experience (TechMahindra) alongside hands-on verification work in Verilog and SystemVerilog. Designed reusable RTL blocks and microarchitecture specifications, integrated third-party IP into top-level module interconnects, managed clock domains, and performed linting, Clock Domain Crossing (CDC) analysis, and basic Static Timing Analysis (STA) to ensure RTL quality – collaborating closely with verification teams to close out functional coverage. Built simulation testbenches and performed functional-equivalence checking against specification (JTAG/TAP controller), and studied formal verification concepts – SystemVerilog Assertions (SVA), temporal-logic properties, and model-checking – through JasperGold/OneSpin coursework and self-study. Delivers RTL projects independently end-to-end: a dual-core RISC-V design with shared-memory arbitration on FPGA, an AXI-Stream digital datapath with pipelined flow control, and a Python-based RTL code generator producing synthesizable Verilog from a structured model. Comfortable in Linux/Git workflows, with FPGA bring-up experience on Zynq-7000/Vivado and exposure to Cadence Virtuoso. Actively expanding into high-speed serial interface design (PCIe, Ethernet, Aurora) and advanced timing-closure work.