Massimiliano Giacometti-Founder and Managing Director, SoC Integration Engineer
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Experience
Founder and Managing Director, SoC Integration Engineer
PlanV
- CVA6 MMU: formal verification using SVA
- CVA6 subsystem: IP integration, verification (UVM)
- Tightly coupled cache coherence for CVA6: RTL design and verification (SystemVerilog), FPGA prototyping (IP integration - CPU, LLC, DDR, Eth), Linux
- Verification of a laser controller on FPGA (medical, VHDL, VUnit, Python, C++ for Microblaze)
- Fault injection emulation on FPGA (SystemVerilog)
Staff Member
OpenHW Group
- DevOps engineer: CI using AWS CodeBuild, GitHub Actions
- Promotional activities: demo application for CORE-V-MCU, OpenHW TV, trade fairs
Freelance Consultant - ASIC Design and Verification
QuantumBlockchainTechnologies
- Responsible for the development of ASIC for crypto mining: definition of the verification architecture, RTL design and testing, synthesis with Cadence Genus, FPGA prototyping
- Interfacing with the teams developing the optimized algorithms, interfacing SDRAM, DDR2 with backender, interfacing with the EDA tool vendors
Head of Hardware Development
HENSOLDT Cyber GmbH
- Definition of the system architecture for the MiG-V chip family, RTL design, IP integration (CPU, Ethernet, SDRAM, flash)
- Logic obfuscation, definition and execution of the test strategy, definition and automation of the workflow
- FPGA prototyping with Yosys, interfacing with EDA tool vendors and backender, GCC interfacing with the software team
- Interfacing with university partners, recruiting, mentoring new employees (VHDL/Verilog/SystemVerilog), reporting to CTO and Chief Scientist
Freelance Consultant
Infineon
- Development of the virtual prototype of smartcard chips (SystemC)
Freelance Consultant
PHLUIDO
- FFT hardware acceleration based on Zynq and related Linux driver (Xilinx Tcl and C)
Freelance Consultant
Mavigex
- Development of S-M2M modulator (C and VHDL)
Freelance Consultant
Intel Mobile Communications
- Development and verification of the firmware and virtual prototype of a DMA: firmware development in Forth, low level simulations with Synopsys VCS
- Design of the virtual prototype in SystemC, interfacing with the hardware development team, participating in chip bringup
Freelance Consultant
Mindway
- BCH and LDPC encoder development for DVB-T2 (VHDL code and C++ model)
- Turbo encoder development for an FSIM modulator (VHDL code and C++ model)
Freelance Consultant
CNIT
- Quantization and modeling in C of a signal detection and synchronization algorithm for satellite communications
FPGA Engineer
Mindway
- RTL development and FPGA implementation of ECC systems (ProMPEG-COP3, block product codes) for broadcasting systems (VHDL and Xilinx Spartan3)
FPGA and Firmware Consultant
Info Solution
- Optimization and FPGA porting of protection management for an optical multi-service node
- Development of a heating measurement system UNI EN 834 compliant (C and assembly for Microchip PIC)
Trainee
TurboConcept
- Development of a VHDL to SystemC and Verilog translation and manipulation tool
Fellowship
University of Parma
- Development of a ZigBee to CANBus interface
Industry experience
See where this freelancer has spent most of their professional time.
Experienced in Information Technology, Manufacturing, Aerospace and Defense, Telecommunication, Media and Entertainment, and Utilities.
Business area experience
See which departments and functions this freelancer has contributed to most.
Experienced in Product Development, Quality Assurance, Research and Development, Information Technology, and Marketing.
Skills
Business Development And Administration
Team Leading
Computer Architecture
Risc-V
Fpga/Asic Design And Verification
Soc Integration
Sdram, Ddr2
Workflow Automation
Xilinx Vivado
Siemens Questa
Synopsys Vcs
Verilator
Synopsys Design Compiler
Synopsys Spyglass
Synopsys Formality
Cadence Genus
Cadence Conformal
Yosys
Gcc
Vhdl/Verilog/Systemverilog
Systemc
C/C++
Python
Perl
Languages
Education
University of Parma
Master of Science in Electronic Engineering · Electronic Engineering · Parma, Italy · 110/110 cum laude
University of Parma
Bachelor of Science in Electronic Engineering · Electronic Engineering · Parma, Italy · 110/110 cum laude
Statistics
Experience
Global experience
Expertise
Qualifications
Profile
Frequently asked questions
Have questions? Find more information here.
Massimiliano is based in Munich, Germany and can operate in on-site, hybrid, and remote work models.
Massimiliano speaks the following languages: Italian (Native), German (Advanced), French (Advanced), Russian (Advanced), English (Elementary).
Massimiliano has at least 20 years of experience. During this time, Massimiliano has worked in at least 9 different roles and for 13 different companies. The average length of individual experience is 1 year and 5 months. Note that Massimiliano may not have shared all experience and actually has more experience.
Based on recent experience, Massimiliano would be well-suited for roles such as: Founder and Managing Director, SoC Integration Engineer, Staff Member, Freelance Consultant - ASIC Design and Verification.
Massimiliano's most recent position is Founder and Managing Director, SoC Integration Engineer at PlanV.
In recent years, Massimiliano has worked for PlanV, OpenHW Group, QuantumBlockchainTechnologies, and HENSOLDT Cyber GmbH.
Massimiliano is most experienced in industries like Information Technology, Manufacturing, and Aerospace and Defense. Massimiliano also has some experience in Telecommunication, Media and Entertainment, and Utilities.
Massimiliano is most experienced in business areas like Product Development, Quality Assurance, and Research and Development. Massimiliano also has some experience in Information Technology and Marketing.
Massimiliano has recently worked in industries like Information Technology, Manufacturing, and Aerospace and Defense.
Massimiliano has recently worked in business areas like Product Development, Research and Development, and Quality Assurance.
Massimiliano holds a Master in Electronic Engineering from University of Parma and a Bachelor in Electronic Engineering from University of Parma.
The availability of Massimiliano needs to be confirmed.
Daily rate distribution
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Average rates for similar positions
Rates are based on recent contracts and do not include FRATCH margin.
The average daily rate is the mean of all daily rates from recent contracts of comparable freelancers on our platform.
The median daily rate is the middle value of all daily rates — half of comparable freelancers charge less, half charge more. Unlike the average, it is barely affected by outliers.
Calculated based on our freelancers’ daily rates as of 7 Sep 2026. Actual rates may vary depending on seniority level, experience, skill specialization, project complexity, and engagement length.
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