Basavaraj Chikkanagoudar - ASIC Design Verification Engineer

Q: Where is Basavaraj based?

Basavaraj is based in Freiburg im Breisgau, Germany .

Q: What languages does Basavaraj speak?

Basavaraj speaks the following languages: English (Advanced), Kannada (Advanced), German (Elementary) .

Q: How many years of experience does Basavaraj have?

Basavaraj has at least 6 years of experience. During this time, Basavaraj has worked in at least 9 different roles and for 4 different companies . The average length of individual experience is 1 year and 8 months . Note that Basavaraj may not have shared all experience and actually has more experience.

Q: What is Basavaraj's latest experience?

Basavaraj's most recent position is ASIC Verification Engineer at Ogheri Consulting GmbH .

Q: What companies has Basavaraj worked for in recent years?

In recent years, Basavaraj has worked for Ogheri Consulting GmbH , MINRES Technologies , Forschungszentrum Informatik (FZI) , and Synopsys .

Q: Which industries is Basavaraj most experienced in?

Basavaraj is most experienced in industries like Information Technology , Agriculture , and Retail . Basavaraj also has some experience in Manufacturing .

Q: Which business areas is Basavaraj most experienced in?

Basavaraj is most experienced in business areas like Information Technology , Product Development , and Quality Assurance . Basavaraj also has some experience in Research and Development .

Q: Which industries has Basavaraj worked in recently?

Basavaraj has recently worked in industries like Information Technology and Manufacturing .

Q: Which business areas has Basavaraj worked in recently?

Basavaraj has recently worked in business areas like Quality Assurance , Information Technology , and Product Development .

Recommended expert

Freiburg im Breisgau, Germany

Check rate

Experience

Apr 2026 - Present

5 months

Munich, Germany

ASIC Verification Engineer

Ogheri Consulting GmbH

Built and configured a highly parameterized UVM environment to validate AMBA APB subsystem.
Developed virtual sequencers to drive synchronized, parallel master-slave sequences ensuring accurate peripheral address decoding and protocol handshake.
Methodologies: UVM, Constrained Random Verification
Tools: Cadence Xcelium, SimVision

Mar 2026 - Mar 2026

1 month

Munich, Germany

Firmware Developer

MINRES Technologies

Architectural Environment & Verification Triage: Built and automated a stable RISC-V verification DevContainer by compiling the DBT-RISE-RISCV simulator with its CMake dependencies, and established a deep Python debugging pipeline to isolate an automated 'I' instruction set test failure down to a shell environment mismatch.

Nov 2025 - Mar 2026

5 months

RISC-V Core implementation & evaluation of SBST

Single-cycle RISC-V RV32I_Zicsr implementation
Testing the core using RISCOF plugins
CLIC integration & wrote assembly test cases to verify CSR access, interrupt priority, and level-sensitive interrupt logic.
Evaluation of SBST on fault-free and fault-injected CLIC.

Jul 2025 - Feb 2026

8 months

Karlsruhe, Germany

Research Assistant

Forschungszentrum Informatik (FZI)

Developed comprehensive Cocotb-based testbenches for verifying different memory architectures for (SPRAM, DPRAM, QPRAM, URAM) by incorporating randomized transactions, functional verification through scoreboards and concurrent stimulus generation.
Verified the functionality of Leaky Integrate-and-Fire (LIF) neuron model by implementing multiple cocotb testcases – covering single calculations, spike generation, idle logic and pipelined input behaviour.

Feb 2023 - Aug 2024

1 year 7 months

Bengaluru, India

Sr. ASIC Digital Engineer

Synopsys

FPGA Prototyping: Ported and prototyped High-Speed Ethernet designs (100G/400G controllers) and Time-Sensitive networking features on HAPS-100 platform (Xilinx Virtex Ultrascale+ FPGA)
Verification & Testing: Conducted pre-silicon verification, functional testing, and performance benchmarking for Hyper DMA (HDMA) feature
System Validation: Debugging device drivers and application code to ensure seamless hardware-software integration.

Sep 2020 - Jan 2023

2 years 5 months

Bengaluru, India

ASIC Digital Engineer

Synopsys

RTL Design & IP Integration: Integrated Ethernet MAC/PCS IPs (1G/10G/40G) with PCIe, AMBA (AXI/APB) protocols, Marvell 1G PHYs, and Xilinx transceivers (GTH/GTY) to build Ethernet solutions.
FPGA Prototyping & Flow: Managed the full FPGA implementation flow – including synthesis, place & route, and timing closure – to validate customer designs on Xilinx Virtex Ultrascale (HAPS-80) platforms.
Verification & Board Bring-up: Developed comprehensive test plans and testbenches for pre-silicon verification, executed software driver tests, and performed hardware board bring-up.
Tools: VCS, Protocompiler, Vivado, Synplify

Jan 2020 - Aug 2020

8 months

Bengaluru, India

Intern

Synopsys

Exposure to the Linux environment, scripting
Got familiar with the prototyping environment, clocking & reset, writing timing constraints, FPGA pin mapping

Jan 2020 - Jun 2020

6 months

Plant Disease Detection

Detection of 15 plant diseases among 3 crops species
CNN technique is deployed to detect diseases
The model is trained to detect healthy & disease plants

Jul 2019 - Dec 2019

6 months

RFID based vending system

Automatic vending system, based on sensors
RFID based payment system

Industry Experience

See where this freelancer has spent most of their professional time.

Experienced in Information Technology, Manufacturing, Agriculture, and Retail.

Information Technology

Manufacturing

Agriculture

Retail

Business Area Experience

See which departments and functions this freelancer has contributed to most.

Experienced in Information Technology, Product Development, Quality Assurance, and Research and Development.

Information Technology

Product Development

Quality Assurance

Research and Development

Summary

FPGA Prototype Engineer with 4 years of experience in the VLSI industry, currently pursuing M.Sc. in Embedded Systems with a focus on Hardware-Software co-design. Leveraging a strong background in pre-silicon verification, hardware bring-up, and complex IP integration to transition into Design Verification. Passionate about innovation, with a strong drive to contribute to cutting-edge projects and push technological boundaries.

Skills

Verilog
System Verilog
C
Python
Uvm
Cocotb
Ethernet (1g-400g)
Amba (Axi, Apb)
Pcie
Xilinx Ips
Synopsys Vcs
Protocompiler
Xilinx Vivado
Cadence Xcelium
Xilinx Virtex Ultrascale And Ultrascale+ (Haps-80 And Haps-100 Platforms)

Languages

English

Advanced

Kannada

Advanced

German

Elementary

Education

Oct 2024 - Present

Albert-Ludwigs-Universität Freiburg

M.Sc. · Embedded Systems · Freiburg im Breisgau, Germany · 1.4

Aug 2016 - Aug 2020

BMS College of Engineering

Bachelor of Engineering · Electronics & Communication · Bengaluru, India · 1.4

Certifications & licenses

Accelerated Verification with UVM

Python CocoTB Fundamentals, OOPS

Udemy

System Verilog Essentials

Udemy

SystemVerilog for Design and Verification

Cadence Design Systems

VLSI CAD Part 1: Logic

University of Illinois, Coursera

Verification with System Verilog and UVM

VeriKwest, Bengaluru

Statistics

Experience

Total positions 9

Experience in Information Technology 6 y

Avg length 9 m

Longest experience 2 y 4 m

Global Experience

Countries worked in 2 (Germany, India)

Primary country Germany

Expertise

Recent roles ASIC Verification Engineer, Firmware Developer, RISC-V Core implementation & evaluation of SBST

Main industries Information Technology, Manufacturing, Agriculture

Main business areas Information Technology, Product Development, Quality Assurance

Qualifications

Highest degree Master

Certifications earned 6

Profile

Created

August 2026

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Frequently asked questions

Have questions? Find more information here.

Basavaraj is based in Freiburg im Breisgau, Germany.

Basavaraj speaks the following languages: English (Advanced), Kannada (Advanced), German (Elementary).

Basavaraj has at least 6 years of experience. During this time, Basavaraj has worked in at least 9 different roles and for 4 different companies. The average length of individual experience is 1 year and 8 months. Note that Basavaraj may not have shared all experience and actually has more experience.

Based on recent experience, Basavaraj would be well-suited for roles such as: ASIC Verification Engineer, Firmware Developer, RISC-V Core implementation & evaluation of SBST.

Basavaraj's most recent position is ASIC Verification Engineer at Ogheri Consulting GmbH.

In recent years, Basavaraj has worked for Ogheri Consulting GmbH, MINRES Technologies, Forschungszentrum Informatik (FZI), and Synopsys.

Basavaraj is most experienced in industries like Information Technology, Agriculture, and Retail. Basavaraj also has some experience in Manufacturing.

Basavaraj is most experienced in business areas like Information Technology, Product Development, and Quality Assurance. Basavaraj also has some experience in Research and Development.

Basavaraj has recently worked in industries like Information Technology and Manufacturing.

Basavaraj has recently worked in business areas like Quality Assurance, Information Technology, and Product Development.

Basavaraj holds a Master in Embedded Systems from Albert-Ludwigs-Universität Freiburg and a Bachelor in Electronics & Communication from BMS College of Engineering.

Basavaraj has 6 certificates. Among them, these include: Accelerated Verification with UVM, Python CocoTB Fundamentals, OOPS, and System Verilog Essentials.

Basavaraj will be available full-time from October 2026.

Basavaraj's rate depends on the specific project requirements. Please use the Meet button on the profile to schedule a meeting and discuss the details.

To hire Basavaraj, click the Meet button on the profile to request a meeting and discuss your project needs.

Daily Rate Distribution

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<€800 €800-1200 €1600+

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Actual rates may vary depending on seniority level, experience, skill specialization, project complexity, and engagement length.

Average rates for similar positions

Rates are based on recent contracts and do not include FRATCH margin.

1000

750

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Daily rate avg. 890 €

The average daily rate is the mean of all daily rates from recent contracts of comparable freelancers on our platform.

1000

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Median rate 800 €

The median daily rate is the middle value of all daily rates — half of comparable freelancers charge less, half charge more. Unlike the average, it is barely affected by outliers.

Actual rates may vary depending on seniority level, experience, skill specialization, project complexity, and engagement length.