Basavaraj (R) Chikkanagoudar-ASIC Design Verification Engineer
Check rate
Experience
ASIC Verification Engineer
Ogheri Consulting GmbH
- Built and configured a highly parameterized UVM environment to validate AMBA APB subsystem.
- Developed virtual sequencers to drive synchronized, parallel master-slave sequences ensuring accurate peripheral address decoding and protocol handshake.
- Methodologies: UVM, Constrained Random Verification
- Tools: Cadence Xcelium, SimVision
Firmware Developer
MINRES Technologies
- Architectural Environment & Verification Triage: Built and automated a stable RISC-V verification DevContainer by compiling the DBT-RISE-RISCV simulator with its CMake dependencies, and established a deep Python debugging pipeline to isolate an automated 'I' instruction set test failure down to a shell environment mismatch.
RISC-V Core implementation & evaluation of SBST
- Single-cycle RISC-V RV32I_Zicsr implementation
- Testing the core using RISCOF plugins
- CLIC integration & wrote assembly test cases to verify CSR access, interrupt priority, and level-sensitive interrupt logic.
- Evaluation of SBST on fault-free and fault-injected CLIC.
Research Assistant
Forschungszentrum Informatik (FZI)
- Developed comprehensive Cocotb-based testbenches for verifying different memory architectures for (SPRAM, DPRAM, QPRAM, URAM) by incorporating randomized transactions, functional verification through scoreboards and concurrent stimulus generation.
- Verified the functionality of Leaky Integrate-and-Fire (LIF) neuron model by implementing multiple cocotb testcases – covering single calculations, spike generation, idle logic and pipelined input behaviour.
Sr. ASIC Digital Engineer
Synopsys
- FPGA Prototyping: Ported and prototyped High-Speed Ethernet designs (100G/400G controllers) and Time-Sensitive networking features on HAPS-100 platform (Xilinx Virtex Ultrascale+ FPGA)
- Verification & Testing: Conducted pre-silicon verification, functional testing, and performance benchmarking for Hyper DMA (HDMA) feature
- System Validation: Debugging device drivers and application code to ensure seamless hardware-software integration.
ASIC Digital Engineer
Synopsys
- RTL Design & IP Integration: Integrated Ethernet MAC/PCS IPs (1G/10G/40G) with PCIe, AMBA (AXI/APB) protocols, Marvell 1G PHYs, and Xilinx transceivers (GTH/GTY) to build Ethernet solutions.
- FPGA Prototyping & Flow: Managed the full FPGA implementation flow – including synthesis, place & route, and timing closure – to validate customer designs on Xilinx Virtex Ultrascale (HAPS-80) platforms.
- Verification & Board Bring-up: Developed comprehensive test plans and testbenches for pre-silicon verification, executed software driver tests, and performed hardware board bring-up.
- Tools: VCS, Protocompiler, Vivado, Synplify
Intern
Synopsys
- Exposure to the Linux environment, scripting
- Got familiar with the prototyping environment, clocking & reset, writing timing constraints, FPGA pin mapping
Plant Disease Detection
- Detection of 15 plant diseases among 3 crops species
- CNN technique is deployed to detect diseases
- The model is trained to detect healthy & disease plants
RFID based vending system
- Automatic vending system, based on sensors
- RFID based payment system
Industry experience
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Experienced in Information Technology, Manufacturing, Agriculture, and Retail.
Business area experience
See which departments and functions this freelancer has contributed to most.
Experienced in Information Technology, Product Development, Quality Assurance, and Research and Development.
Summary
FPGA Prototype Engineer with 4 years of experience in the VLSI industry, currently pursuing M.Sc. in Embedded Systems with a focus on Hardware-Software co-design. Leveraging a strong background in pre-silicon verification, hardware bring-up, and complex IP integration to transition into Design Verification. Passionate about innovation, with a strong drive to contribute to cutting-edge projects and push technological boundaries.
Skills
- Verilog
- System Verilog
- C
- Python
- Uvm
- Cocotb
- Ethernet (1g-400g)
- Amba (Axi, Apb)
- Pcie
- Xilinx Ips
- Synopsys Vcs
- Protocompiler
- Xilinx Vivado
- Cadence Xcelium
- Xilinx Virtex Ultrascale And Ultrascale+ (Haps-80 And Haps-100 Platforms)
Languages
Education
Albert-Ludwigs-Universität Freiburg
M.Sc. · Embedded Systems · Freiburg im Breisgau, Germany · 1.4
BMS College of Engineering
Bachelor of Engineering · Electronics & Communication · Bengaluru, India · 1.4
Certifications & licenses
Accelerated Verification with UVM
Python CocoTB Fundamentals, OOPS
Udemy
System Verilog Essentials
Udemy
SystemVerilog for Design and Verification
Cadence Design Systems
VLSI CAD Part 1: Logic
University of Illinois, Coursera
Verification with System Verilog and UVM
VeriKwest, Bengaluru
Statistics
Experience
Global experience
Expertise
Qualifications
Profile
Frequently asked questions
Have questions? Find more information here.
Basavaraj is based in Freiburg im Breisgau, Germany.
Basavaraj speaks the following languages: English (Advanced), Kannada (Advanced), German (Elementary).
Basavaraj has at least 6 years of experience. During this time, Basavaraj has worked in at least 9 different roles and for 4 different companies. The average length of individual experience is 1 year and 8 months. Note that Basavaraj may not have shared all experience and actually has more experience.
Based on recent experience, Basavaraj would be well-suited for roles such as: ASIC Verification Engineer, Firmware Developer, RISC-V Core implementation & evaluation of SBST.
Basavaraj's most recent position is ASIC Verification Engineer at Ogheri Consulting GmbH.
In recent years, Basavaraj has worked for Ogheri Consulting GmbH, MINRES Technologies, Forschungszentrum Informatik (FZI), and Synopsys.
Basavaraj is most experienced in industries like Information Technology, Agriculture, and Retail. Basavaraj also has some experience in Manufacturing.
Basavaraj is most experienced in business areas like Information Technology, Product Development, and Quality Assurance. Basavaraj also has some experience in Research and Development.
Basavaraj has recently worked in industries like Information Technology and Manufacturing.
Basavaraj has recently worked in business areas like Quality Assurance, Information Technology, and Product Development.
Basavaraj holds a Master in Embedded Systems from Albert-Ludwigs-Universität Freiburg and a Bachelor in Electronics & Communication from BMS College of Engineering.
Basavaraj has 6 certificates. Among them, these include: Accelerated Verification with UVM, Python CocoTB Fundamentals, OOPS, and System Verilog Essentials.
Basavaraj will be available full-time from October 2026.
Daily rate distribution
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Calculated based on our freelancers’ daily rates as of 30 Aug 2026. Actual rates may vary depending on seniority level, experience, skill specialization, project complexity, and engagement length.
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