Tien V.-Digital Design Engineer
Check rate
Experience
Staff Digital Design Engineer
Qorvo
- Lead RTL design for PMIC, PLP, PAC IC, ensuring compliance with industry standards.
- Deploy workflows for register mapping, state machine generation, and RTL module connections.
- Utilize JasperGold tools for formal verification, achieving RTL signoff through FPV, SuperLint, and CDC.
- Implement ECO changes, conduct simulation debug, and perform formal verification between synthesis/PNR netlist and updated RTL.
- Collaborate with cross-functional teams to refine design specifications, review verification results, and execution.
- Innovation award for CDC solution using Candece HAL
Staff FPGA Engineer
SoC.One
- Developed RISC-V SoC acceleration solutions, enhancing application performance.
- Designed and deployed RISC-V debug/trace IP cores for various CPU architectures using XDMA IP on AMD boards.
- Integrated Gigabit Ethernet support on Terasic/Intel boards using LiteEth framework.
- Implemented vector support for CV32E40P, improving computational efficiency.
- Streamlined validation processes using Siemens Veloce/Primo emulator.
- Executed Virtual JTAG as RISC-V Debug Transport Module on Intel boards, eliminating need for physical debug probes.
- Enhanced RISC-V debug performance by replacing low-speed JTAG RISCV DTM with high-speed PCIe using LitePCIe core supporting multiple harts debugging.
- Integrate BOOM core in Litex frameworkd and support out of order debugging for BOOM
Senior Technical Leader
HCL Technologies
- Led development of Encoder Divided-Output and System Control modules for ARM-based microprocessor projects.
Senior FPGA engineer
Vinsmart JSC
- Led development of 5G Remote Radio Unit with emphasis on Fronthaul Subsystem design and integration.
- Managed Ethernet 10/25G IP development alongside ORAN framer, deframer, and encoding functionality, ensuring robust performance.
- Integrated JESD204B Multi-Gigabit serial data link for Analog Device ADC/DAC and FPGA devices.
- Constructed SystemVerilog simulation environment incorporating ORAN, Low PHY, and DFE functions for comprehensive system testing.
- Collaborated effectively with hardware and firmware teams to achieve seamless system integration and troubleshooting.
Digital Design & Verification Engineer
Toshiba Vietnam (TSDV)
- Participated in automotive MCU development with a focus on verification planning for complex bus systems, including AMBA and in-house buses.
- Defined formal and simulation verification environments utilizing vendor VIP and auxiliary logic.
- Executed comprehensive verification plans by creating verification patterns and SystemVerilog Assertions (SVAs).
- Conducted debugging and coverage analysis, delivering detailed reports on IP/system level functional verification for Code Flash Memory and multi-core support modules.
- Collaborated closely within a 5-member team to enhance verification processes and drive project success.
- Participating in High Level Synthesis on Xilinx FPGA development team Team size 6 members Tuning C/C++ source code for adapting Xilinx HLS coding style Execution and evaluation performance of application on Xilinx ZC702 development kit Transform algorithm from C/C++ to Verilog Unit verification using SystemVerilog DPI-C
- Best team, best engineer award
Industry experience
See where this freelancer has spent most of their professional time.
Experienced in Information Technology, Automotive, and Telecommunication.
Business area experience
See which departments and functions this freelancer has contributed to most.
Experienced in Information Technology, Product Development, and Quality Assurance.
Summary
Dynamic Senior Digital Design Engineer with over 10 years of experience in ASIC and FPGA design and verification. Expertise encompasses RTL design, formal verification, and cross-functional collaboration to refine specifications and drive project success. Proficient in advanced technologies including 5G, ORAN, Ethernet, PCIe, and various bus protocols, while leveraging industry-standard EDA tools for robust design and verification processes. Committed to mentoring and optimizing design flows.
Skills
- Asic/Fpga Digital Design And Verification
- Verilog, Systemverilog
- 5g, Oran, Ethernet
- 10/25g, Jesd204
- Dma, Xdma
- Litepcie, Liteeth
- Liteuart, Litespi
- Bus Protocol (Axi3, Axi4, Axi4 Stream, Apb, Avalon, Wishbone, Spi, I2c, Uart)
- Python Migen, Litex
- Cocotb, Scala, Chisel
- Fpga (Xilinx, Intel)
- Riscv, External Debug, Processor Trace, Vector Extension
- Formal Verification, Uvm, Register Model
- Scripting (Bash, Cshell, Python)
- Eda Tools (Vcs, Verdi, Spyglass, Vc-Formal, Xcelium, Simvision, Jaspergold, Questasim, Vivado, Quartus, Verilator)
- Executed Rtl Coding, Linting, Synthesis, And Verification Processes While Adhering To Best Practices.
- Collaborated With Cross-Functional Teams To Optimize System Design And Enhance Performance Metrics.
- Developed Comprehensive Verification Plans, Scenarios, And Systemverilog Assertions (Sva).
- Mentored Junior Engineers On Vlsi Design Flow And Best Practices In Digital Design.
- Implemented Design Reviews And Performance Benchmarks To Ensure Adherence To Project Specifications.
- Enhanced Debugging Strategies To Identify And Resolve Design Issues Efficiently.
- Best Effort Engineer In Vlsi Domain
Languages
Education
VNU University of Engineering and Technology
Bachelor · Viet Nam
Statistics
Experience
Global experience
Expertise
Qualifications
Profile
Frequently asked questions
Have questions? Find more information here.
Tien is based in Hanoi, Viet Nam.
Tien speaks the following languages: Vietnamese (Native), English (Advanced).
Tien has at least 11 years of experience. During this time, Tien has worked in at least 5 different roles and for 5 different companies. The average length of individual experience is 2 years and 2 months. Note that Tien may not have shared all experience and actually has more experience.
Based on recent experience, Tien would be well-suited for roles such as: Staff Digital Design Engineer, Staff FPGA Engineer, Senior Technical Leader.
Tien's most recent position is Staff Digital Design Engineer at Qorvo.
In recent years, Tien has worked for Qorvo, SoC.One, and HCL Technologies.
Tien is most experienced in industries like Information Technology, Automotive, and Telecommunication.
Tien is most experienced in business areas like Information Technology, Product Development, and Quality Assurance.
Tien has recently worked in industries like Information Technology.
Tien has recently worked in business areas like Information Technology and Product Development.
Tien holds a Bachelor from VNU University of Engineering and Technology.
The availability of Tien needs to be confirmed.
Daily rate distribution
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Average rates for similar positions
Rates are based on recent contracts and do not include FRATCH margin.
The average daily rate is the mean of all daily rates from recent contracts of comparable freelancers on our platform.
The median daily rate is the middle value of all daily rates — half of comparable freelancers charge less, half charge more. Unlike the average, it is barely affected by outliers.
Calculated based on our freelancers’ daily rates as of 9 Oct 2026. Actual rates may vary depending on seniority level, experience, skill specialization, project complexity, and engagement length.
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