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Experience
Jan 2024 - Jul 2026
2 years 7 monthsTehran, Iran, Islamic Republic of
Senior FPGA Engineer
SE Corporation
Position Summary
Senior FPGA Engineer at SE Corporation
Industries
Information Technology
Telecommunication
Business Areas
Information Technology
Product Development
Project Management
Research and Development
- Led 5 FPGA engineers across 4 SDR projects—orchestrating architecture, integration, and validation. Delivered all on schedule with zero late-stage integration failures while mentoring two juniors to independent ownership.
- Engineered JESD204B/C interfaces on Zynq MPSoC, 7Series, and Zynq APSoC devices, achieving error-free up to 9.830 Gbps (Rx) and 4.915 Gbps (Tx) line rate. Furthermore, PHY integration and clock management, resolving complex synchronization of Reference, Core, and Interface clocks across 4 different platforms with 4 different scenarios.
- Architected dual-MicroBlaze asymmetric multiprocessing system, one for SPI/I2C peripheral control and command sequencing, another for floating-point DSP algorithms (ported from MATLAB). This led to cutting resource usage, accelerating throughput, and reducing debugging time from weeks to 3-4 days through fast software simulation of the floating-point core.
- Designed AGC receiver front-end using Vitis HLS—leveraging resource sharing to handle high bit-width calculations while achieving proper performance with optimized resource usage (~10% reduction in FPGA utilization).
- Designed high-rate CIC filter using MATLAB code generation—overcame Xilinx IP core's 48-bit limit to support 58-bit precision with comparable timing and resource utilization.
Jan 2024 - May 2026
2 years 5 monthsTehran, Iran, Islamic Republic of
Chief Technology Officer (CTO) | Head of R&D
OTICAMP
Position Summary
Chief Technology Officer (CTO) | Head of R&D at OTICAMP
Industries
Information Technology
Telecommunication
Business Areas
Information Technology
Product Development
Research and Development
- Implemented DMA/Scatter-Gather data paths and integrated FPGA logic with ADCs/DACs, RF transceivers, and memory across four platforms.
- Led multidisciplinary engineering teams including FPGA, RF, embedded Linux, and MATLAB developers, improving cross-team collaboration and accelerating project delivery timelines
- Closed timing, completed place and route, and validated FPGA builds to improve readiness and reduce late-stage integration risk.
- Established development work flows, using git, issue tracking systems.
Feb 2018 - Dec 2024
6 years 11 monthsTehran, Iran, Islamic Republic of
Senior FPGA / SoC and Embedded System Developer and Team Lead
ICI
Position Summary
Senior FPGA / SoC and Embedded System Developer and Team Lead at ICI
Industries
Information Technology
Business Areas
Information Technology
Product Development
- Engineered Viterbi (constraint length 7) and BCJR decoders using pipelined sliding window technique across multiple memories—decoupling forward/backward paths to handle high data rates without large buffers. Achieved deterministic latency under worst-case conditions.
- Architected parallel Walsh coding engine using interleaved memory storage to enable multi-block parallel access—saving block RAM resources while maintaining throughput.
- Engineered cascaded SerDes (2 blocks, 12:1, 380 MHz) on Virtex-6/7—resolved Tx/Rx sync using bit-slipping to align 12-bit boundaries. Delivered stable links across both platforms.
- Engineered custom embedded Linux for Zynq-7020 modem platform—kernel config, device tree, bootloader, and root filesystem. Integrated OLED driver as kernel module, resolved SPI interrupt issues via device tree. Delivered stable platform for modem UI and external communication—accelerating app development and time-to-market.
Jun 2016 - Jan 2024
7 years 8 monthsTehran, Iran, Islamic Republic of
Senior FPGA Engineer/SoC developer
ICI
Position Summary
Senior FPGA Engineer/SoC developer at ICI
Industries
Information Technology
Telecommunication
Business Areas
Information Technology
Product Development
Quality Assurance
- Developed floating-point FPGA accelerators in PL to offload compute-intensive processing from PS and improve system-level performance.
- Resolved complex timing violations across multiple projects on Artix-7 using: multi-cycle paths (3-4 cycles for computation blocks), fan-out optimization (relaxing loaded registers), and critical path restructuring (breaking long paths with parallel flip-flops). Achieved timing closure at 200 MHz without major architectural changes.
- Established systematic timing methodology across 6 projects: early definition of clock/reset/control scenarios, isolated clock domains with dedicated CDC, local self-initialized control signals, and strategic constraints. Achieved predictable timing closure with zero last-minute surprises.
- Engineered DQPSK/QPSK modulator/demodulator for SDR—implemented full chain including carrier/timing recovery. Achieved low BER under varying SNR.
- Architected Polyphase, FIR, and IIR filters for SDR—optimizing for rates from 192 kHz to 192 MHz Parallel for high-rate, serial/semi-parallel for lower-rate with up to 90% resource savings. Implemented interleaved/dual-port memory for multi-channel sharing.
- Engineered zero-IF up/down conversion for SDR—overcame high ADC sample rate timing challenges using CIC decimation (high bit-width), NCO-based mixing (large lookup tables), and FIR filtering for clock domain crossing. Achieved stable timing closure and optimal resource utilization.
- Orchestrated SDR system integration and validation—spanning FPGA and product level Developed structured testing (corner-case scenarios, ILA debugging, custom flags for memory limited monitoring, MATLAB golden reference validation). Delivered production-ready system with zero field surprises.
Nov 2010 - May 2016
5 years 7 monthsTehran, Iran, Islamic Republic of
FPGA Engineer
ICI
Position Summary
FPGA Engineer at ICI
Industries
Information Technology
Business Areas
Information Technology
- Implemented fixed-point and floating-point mathematical blocks, including square-root and logarithm units, for FPGA-based compute acceleration.
- Developed NCO-based frequency-synthesis logic for accurate tone generation and signal processing.
- Designed up/down-conversion modules for digital RF chains, optimizing latency, signal flow, and resource usage.
Industry Experience
See where this freelancer has spent most of their professional time.
Experienced in Information Technology and Telecommunication.
Information Technology
Telecommunication
Business Area Experience
See which departments and functions this freelancer has contributed to most.
Experienced in Information Technology, Product Development, Quality Assurance, Project Management, and Research and Development.
Information Technology
Product Development
Quality Assurance
Project Management
Research and Development
Languages
English
Advanced Persian
Advanced Education
K. N. Toosi University of Technology
Master's Degree · Electrical Engineering · Tehran, Iran, Islamic Republic of
Hakim Sabzevari University
B.Sc. · Electrical Engineering · Iran, Islamic Republic of
Statistics
Experience
Total positions 5
Experience in Information Technology 15.5 y
Avg length 4 y 11 m
Longest experience 7 y 7 m
Global Experience
Countries worked in 1 (Iran, Islamic Republic of)
Primary country Iran, Islamic Republic of
Expertise
Recent roles Senior FPGA Engineer, Chief Technology Officer (CTO) | Head of R&D, Senior FPGA / SoC and Embedded System Developer and Team Lead
Main industries Information Technology, Telecommunication
Main business areas Information Technology, Product Development, Quality Assurance
Qualifications
Highest degree Master
Profile
Created
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speaks the following languages: English (Advanced), Persian (Advanced).
has at least 16 years of experience. During this time, has worked in at least 5 different roles and for 3 different companies. The average length of individual experience is 3 years and 2 months. Note that may not have shared all experience and actually has more experience.
Based on recent experience, would be well-suited for roles such as: Senior FPGA Engineer, Chief Technology Officer (CTO) | Head of R&D, Senior FPGA / SoC and Embedded System Developer and Team Lead.
's most recent position is Senior FPGA Engineer at SE Corporation.
In recent years, has worked for SE Corporation, OTICAMP, and ICI.
is most experienced in industries like Information Technology and Telecommunication.
is most experienced in business areas like Information Technology, Product Development, and Quality Assurance. also has some experience in Project Management and Research and Development.
has recently worked in industries like Information Technology and Telecommunication.
has recently worked in business areas like Information Technology, Product Development, and Quality Assurance.
holds a Master in Electrical Engineering from K. N. Toosi University of Technology and a Bachelor in Electrical Engineering from Hakim Sabzevari University.
will be available full-time from October 2026.
's rate depends on the specific project requirements. Please use the Meet button on the profile to schedule a meeting and discuss the details.
To hire , click the Meet button on the profile to request a meeting and discuss your project needs.
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